The Universal Serial Bus (USB) specification is an industry-defined interface for connecting peripherals to the system bus of a personal computer. USB features a single interface for a wide variety of peripherals, including mice, keyboards, monitors, printers, mass storage drives, modems, faxes, and the like. This reduces manufacturing costs and makes it easier for personal computer users to configure their systems.
USB uses a token-based bus architecture, similar to other similarly-based buses such as the token ring network. A USB host broadcasts tokens on the bus, and a USB device that matches an address contained in a token responds either by sending data to the host or accepting data from the host.
To enhance the functional versatility, a USB device can support multiple logical channels of communication with the host. In the parlance of the USB specification, such logical channels are referred to as "pipes." Each pipe provides a unidirectional flow of data between a software client resident in the host and an endpoint defined within the device. Functions implemented within the device receive data from the host at their respective endpoint(s), and transmit data to the host by writing to their respective endpoint(s).
A USB device 10 is shown schematically in FIG. 10. Data is communicated over a pair of differentially driven signal lines D+, D-. A serial interface engine (SIE) 12 provides packet generation and decoding, NRZI conversion, CRC generation and verification, and bit stuffing, all in accordance with the USB specification. A controller 14 handles the data flow for the various transactions, namely IN, OUT and SETUP. As shown in FIGS. 11A and 11B, a transaction comprises up to three packets: TOKEN, DATA, and HANDSHAKE. A bus transaction begins with the host issuing a TOKEN-type packet comprising a PID field, an address field which identifies the device, and an endpoint field which identifies a channel within the device. This is followed by a DATA-type packet, flowing in a direction from the addressed device to the host, FIG. 11A, or from the host to the addressed device, FIG. 11B. In the latter case, the data received by the device is stored in a FIFO corresponding to the endpoint identified in the TOKEN packet. The recipient of the data then transmits a HANDSHAKE protocol to the transmitter of the data.
Returning to FIG. 10, typical implementations of a USB device include a bank of n FIFO's 16, allocating one FIFO (FIFO.sub.1 -FIFO.sub.n) for each endpoint E1-En supported by the device software 18. For example, the Intel.RTM. x8930Ax USB microcontroller chip defines six endpoints, each having an associated transmit FIFO and receive FIFO. The Cypress CY7C634xx family of controllers appear to support two device addresses: "A" and "B". Device address "A" has three associated endpoints while device "B" has two associated endpoints, each endpoint having a corresponding FIFO. The Xilinx.RTM. controller features support for three endpoints, with on-chip FIFO's for each endpoint. A more flexible alternative is one by CAE Technology which offers a function core for FPGAs. The function core features a user definable number of endpoints, and a FIFO for each endpoint having a user definable depth.
Continuing with FIG. 10, the device software 18 provides the functional capabilities of the device. Each functionality communicates with its associated endpoint E1-En, receiving or transmitting data via the FIFOs corresponding to those endpoints. A special endpoint, endpoint 0, is reserved for the purpose of providing access to the device's configuration, status, and control information.
The above-mentioned designs share the common trait in that the number of endpoints possible in a device is fixed. This is true even for the CAE Technology function core. Although the CAE function core provides a user definable number of endpoints, that number is fixed once the design is committed to silicon.
Increasing the number of endpoints in a given design brings up another shortcoming of these design approaches, namely the silicon real estate consumed to support the FIFO's becomes prohibitive since each endpoint requires a FIFO. This is especially true with the INTEL.RTM. design where each endpoint is associated with two FIFO's, one for receive and the other for transmit.
What is needed is a controller that, once designed and tested, is capable of supporting any number of endpoints in a device, up to the USB-defined maximum of sixteen. It is desirable that the controller exhibit efficient use of silicon while at the same time be readily configurable to use any number of endpoints.
Another feature of USB is its support for a technique known as bus enumeration, wherein the host identifies and configures a device upon its attachment to the bus. When the device has been detected by the host, the system software interrogates the device, determines its capabilities, assigns a device address, and configures the device. Although USB provides for situations in which a device is no longer able to communicate with the host, it would be desirable for the device to be completely rebooted so that the host can reconfigure the device as if the device had just been attached to the host by a user.